This invention relates generally to semiconductor devices having conductor-insulator layers formed thereon and more specifically to integrated circuits having dense multilayer metallization. The invention also relates to a method of manufacturing such semiconductor devices and integrated circuits.
As the number of devices on an integrated circuit increases, the complexity of interconnecting the devices often exceeds the capability of providing a corresponding interconnecting pattern on a single conductive layer. Thus the denser integrated circuits have now required the use of two or more conductive layers to provide the required interconnections, with the two or more conductive layers being separated, except for small portions thereof that are electrically interconnected, by an electrically insulating layer. Usually the interconnecting conductive layers are formed of metal in order to reduce the electrical resistance of the conductive layers or lines.
One problem that has been well recognized in, for example, double metal layer devices is the lack of reliability in obtaining continuity of the upper layer metal and integrity of the dielectric insulating layer over the steps formed by the first layer metallization pattern. The problem arises from the difficulty in maintaining an adequately thick metal layer and a stress-free dielectric insulating layer over a step. Moreover, the step edge tends too form voids that can trap an unwanted substance and cause contamination and reliability problems.
A semiconductor device described in U.S. Pat. No. No. 4,360,823, issued Nov. 23, 1982 to VanGils, attempts to address this problem by partially sinking the first metallization pattern into a first insulating layer. The top surface of the first metallization pattern appears to coincide substantially with that of the first insulating layer. The first metallization pattern and the first insulating layer are covered with a second insulating layer and a second metallization pattern is provided on top of the second insulating layer. However, only the second metallization pattern is connected to the semiconductor zones of the semiconductor body via contact windows that extend through the second insulating layer.
A significant disadvantage of this device is that the first metallization pattern is not electrically connected to any of the active semiconductor regions. This means that the circuit layout freedom is strictly and severely limited. For high-packing-density VLSI circuits this limitation is not easily tolerated.
A further disadvantage is that the method disclosed to deposit the aluminum metal layer into the grooves formed by the apertures of the pattern is only applicable to a large aperture. For dense circuits having a geometry size of the order of two (2) micrometers or less, the disclosed method may result in voids in the deposited aluminum within the groove, with conventional metal deposition techniques.
Another disadvantage is that the method disclosed in the above identified patent of selectively removing the metal layer while still leaving the grooves filled is not easily reproducible due to the difficulty of controlling this method.
A still further disadvantage is that this device is limited to only two metallization layers, since a third layer disposed over the uneven surface of the second metal layer will produce the same problems as those discussed above.
An additional problem typical of present day devices using two conductive interconnection layers is the difficulty of defining small metal pitch. Pitch is here defined as the sum of the width of the metal line and its separation from an adjacent line as seen in a plan view. Lift-off techniques have been used to define a smaller pitch, however, there are serious problems in controlling the process to insure repeatability. For example, the pitch that can be achieved using lift-off techniques is limited to no less than 3 micrometers. In general, the width of the metal lines will be limited by the photolithographic techniques which define the pattern. Also, the thickness of the conductive layer will be limited by the step discontinuities over which the patterned metal passes, Thus, a need exists to provide a structure and process which allows an increase in the complexity and yield using metal interconnections in integrated circuits.